H tree

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The first ten levels of an H tree

The H tree (so called because its first two steps resemble the letter "H") is a family of fractal sets whose Hausdorff dimension is equal to 2. They can be constructed by starting with a line segment of arbitrary length, drawing two shorter segments at right angles to the first through its endpoints, and continuing in the same vein, reducing the length of the line segments drawn at each stage by √2. Surprisingly, continuing this process will eventually result in a rectangle, or in other words, the H-fractal is a Peano curve. It is also an example of a fractal canopy, in which the angle between neighboring line segments is always 180 degrees.

An alternative process that generates the same fractal set is to begin with a silver rectangle[1] and repeatedly bisect it into two smaller silver rectangles, at each stage connecting the two centroids of the two smaller rectangles by a line segment. A similar process can be performed with rectangles of any other shape, but the silver rectangle leads to the line segment size decreasing uniformly by a √2 factor at each step while for other rectangles the length will decrease by different factors at odd and even levels of the recursive construction.

The Mandelbrot Tree is a very closely related fractal using rectangles instead of line segments, slightly offset from the H-tree positions, in order to produce a more naturalistic appearance. To compensate for the increased width of its components and avoid self-overlap, the scale factor by which the size of the components is reduced at each level must be slightly greater than √2.

Applications

The H tree is commonly used in VLSI design as a clock distribution network for routing timing signals to all parts of a chip with equal propagation delays to each part.[2] Additionally, the H tree has been used as an interconnection network for VLSI multiprocessors,[3] as a space efficient layout for trees in graph drawing,[4] and as part of a construction of a point set for which the sum of squared edge lengths of the traveling salesman tour is large.[5]

Notes

  1. That is, a rectangle with sides in the ratio 1:√2, such as is used for A4 paper.
  2. Ullman (1984); Burkis (1991).
  3. Browning (1980). See especially Figure 1.1.5, page 15.
  4. Nguyen and Huang (2002).
  5. Bern and Eppstein (1993).

References

  • Burkis, J. (1991). "Clock tree synthesis for high performance ASICs". IEEE International Conference on ASIC: 9.8.1–9.8.4. DOI:10.1109/ASIC.1991.242921. 
  • Nguyen, Quang Vinh; Huang, Mao Lin (2002). "A space-optimized tree visualization". IEEE Symposium on Information Visualization: 85–92. DOI:10.1109/INFVIS.2002.1173152. 

External links